While there are hardware-based security solutions that are based on cryptography, there are no commercial products that provide comprehensive security solutions implemented in hardware. We believe that our products will make unique contributions to the security sector and observe massive move forward hardware-assisted security.
The technical innovation in hardware 2.0 spans over several areas. In order to support such diverse robust security solutions against well-organized intelligent attacks, embedded co-processing systems should be equipped with dedicated high-performance reprogrammable hardware engine within a limited cost, especially computation resources and power consumption. Thus the architecture of this hybrid co-processor platform should be continuously innovated considering at least following facts through the current Phase-I products and services as shown in the below figure.
Hybrid Architecture: A critical task towards designing hybrid co-processor such as Manycore-CPU-Hardwired systems is in understanding the characteristics of various workloads and traffic imposed by a diverse set of objectives and in monitoring intrusion, detecting anomaly, preventing unauthorized access, and securing root. Towards accomplishing this important task, we have been developing architectural frameworks on various systems and configurations including the below experimental platform. We conducted technical research and data collection, or participate in working group meetings with reviewing technical documentation and data analysis.
Feature of Emerging Trends in Hardware 2.0 based Architecture: The future target architecture of the proposed methodology, as illustrated in the below block diagram consists of a small number of powerful processors, several I/O interfaces, a small module of reconfigurable logic, and a programmable hardware accelerator. The powerful processors take charge of controlling and coordinating the remaining hardware components and executing the software applications. The essence of the proposed architecture is, of course, the programmable hardware accelerator, which is incarnated as a multitude of small processor cores and global logic in support of the new programming model.