• • It is the first to introduce the concept of Asymmetric Coprocessor Hardware Platform and its application to information security. We have succeeded in developing the first commercial products with game changing innovation Web-anomaly detection HW engine, Server BlackBox, and Hardware-Assisted Intrusion Monitoring System (HAIMS™).
  • • Hardware-assisted protection engine and Append-only Storage (AoS) [U.S. and PCT patents pending] is attachable to the host system through PCI, PCIe, SATA, SAS or any other standard interface.
  • • Extending our product line-up to desktops and mobile devices, the hardware engine can also be merged with external interfaces and peripherals such as network card, network adapter of desktop PC.
  • • It provides not only intrusion detection, digital forensic DB for remediation but also contents filtering for prevention, recovery and immuno-engineering. Contents filtering is working in both ways; inward and outward. Inward traffic has inspected and protected against malware, virus malicious process and attacks. Outward filtering get involved to block information leakage, preventing unauthorized transfer.
  • • Our solution provides unique, robust and innovate fundamental as a revolutionary solid security solution. It’d the norm of end point entering a new security world.

The technical innovation in hardware 2.0 spans over several areas. In order to support such diverse robust security solutions against well-organized intelligent attacks, embedded co-processing systems should be equipped with dedicated high-performance reprogrammable hardware engine within a limited cost, especially computation resources and power consumption. Thus the architecture of this hybrid co-processor platform should be continuously innovated considering at least following facts through the current Phase-I products and services as shown in the below figure.

  • Asymmetric manycore architecture even in embedded security to exploit the high-degree of parallelism, but need to consider the heterogeneity and dependency of the applications (tasks)
  • Application specific hardware acceleration, but it must be reconfigurable (or reprogrammable)
  • MPPA-based parallel computing architecture
  • Very low latency communication latency and high bandwidth
  • No performance degradation
  • Easy debugging and reconfigurable feature
  • Hybrid Architecture: A critical task towards designing hybrid co-processor such as Manycore-CPU-Hardwired systems is in understanding the characteristics of various workloads and traffic imposed by a diverse set of objectives and in monitoring intrusion, detecting anomaly, preventing unauthorized access, and securing root. Towards accomplishing this important task, we have been developing architectural frameworks on various systems and configurations including the below experimental platform.
    We conducted technical research and data collection, or participate in working group meetings with reviewing technical documentation and data analysis.

    Feature of Emerging Trends in Hardware 2.0 based Architecture: The future target architecture of the proposed methodology, as illustrated in the below block diagram consists of a small number of powerful processors, several I/O interfaces, a small module of reconfigurable logic, and a programmable hardware accelerator. The powerful processors take charge of controlling and coordinating the remaining hardware components and executing the software applications. The essence of the proposed architecture is, of course, the programmable hardware accelerator, which is incarnated as a multitude of small processor cores and global logic in support of the new programming model.